(a) Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the semiconductor device.
(b) Description of the Related Art
As the semiconductor device has been highly integrated, number of metal wirings increases and the pitch of each metal wiring become reduced. The reduction of pitch causes to increase resistance of the metal wiring and to create a parasite capacitor structure by the inter metal dielectric (IMD) for isolating the metal wirings of the semiconductor and the metal wiring itself, that deteriorate the characteristic of the semiconductor device. That is, the RC constant value determining a response speed of the semiconductor device increases and the power consumption increases.
Accordingly, an IMD having low dielectric constant appropriate for highly integrated semiconductor device has been required and recently fluorine silicate glass (FSG) is used as the low dielectric constant IMD in place of the conventional un-doped silica glass IUSG.
Unlike the conventional USG, in case of using the fluorine-added FSG for maintaining the low dielectric constant a block layer should be formed between the metal wirings and the FSG for protecting movement of the fluorine because the fluorine has high mobility. However, if the block layer formed having defect, the fluorine can be changed into HF due to the hydrogen (H) existing with heat and impurity generated in following process so as to penetrate to damage AL.
In this case a via resistance increases and a metal bridge is created so as to degrade the reliability and yield of the semiconductor devices.
The U.S. Pat. Nos. 6,376,360, U.S. Pat. No. 6,284,677, and U.S. Pat. No. 6,217,658 have disclosed the techniques for protecting the low metal layer with a spread protection layer formed in a single layered structure and using the sidewalls.